_______________
| MEM CONTROL |
| READ |
| CYCLE |
_______________
|
|
↓
__________________________
| mem control flags set: |
| DOING READ ← 1 |
| MEM 0 RQ ← 1 |
| MEM 1 RQ ← 1 |
| MEM INT FREE ← 0 |
| {C0} |
__________________________
|
|
↓
_______________________________________
| Send address to memories from the |
| FETCH register (low bits) and the |
| MEM READ ADDRS register (high bits) |
_______________________________________
|
|
|(follow both branches)
BUS #0 | BUS #1
____________________________________________________________
| |
↓ ↓
_______________________ ________________________
ADDRS ACK (BUS 0) ADDRS ACK (BUS 1)
_______________________ ________________________
| |
↓ ↓
__________________ ________________
| MEM 0 RQ ← 0 | | MEM 1 RQ ← 0 |
__________________ ________________
| |
↓ ↓
__________________________ ____________________________
first RD RSTRT (BUS 0) first RD RSTRT (BUS 1)
__________________________ ____________________________
| |
| |
_______________________ _________________________
|BUS #0 |BUS #0 |BUS #1 |BUS #1
|ADDRS TO MEM 35(0) |ADDRS TO MEM 35(1) |ADDRS TO MEM 35(0) |ADDRS TO MEM 35(1)
| | | |
↓ ↓ ↓ ↓
_______________ _______________ _______________ _______________
| strobe data | | strobe data | | strobe data | | strobe data |
| into BUF 0 | | into BUF 1 | | into BUF 2 | | into BUF 3 |
_______________ _______________ _______________ _______________
| | | |
| | | |
----------→|←---------- --------------------→|←--
| |
| |
______________________ ____________________________
| | | |
|FETCH ADDRS 34(1) |FETCH ADDRS 34(0) |FETCH ADDRS 34(1) |FETCH ADDRS 34(0)
| | | |
| ↓ ↓ |
| ______________________ ________________________ ______________________ |
| | READ AROUND RQ ← 1 |....| RQ will be turned |......| READ-AROUND RQ ← 1 | |
| ______________________ | off when cycle taken | ______________________ |
| | ________________________ | |
| | | |
---------→|←---------- ---------→|←--------------
| |
↓ ↓
___________________________ ______________________________
second RD RSTRT (BUS 0) second RD RSTRT (BUS 1)
___________________________ ______________________________
| |
| |
| |
_______________________ ___________________________
| | | |
|BUS #1 |BUS #1 |BUS #2 |BUS #2
|ADDRS TO MEM 35(0) |ADDRS TO MEM 35(1) |ADDRS TO MEM 35(0) |ADDRS TO MEM 35(1)
| | | |
↓ ↓ ↓ ↓
_______________ _______________ _______________ _______________
| strobe data | | strobe data | | strobe data | | strobe data |
| into BUF 1 | | into BUF 0 | | into BUF 3 | | into BUF 2 |
_______________ _______________ _______________ _______________
| | | |
| | | |
---------→|←--------- ------------------→|←------
| | ------------------------
↓ | ↓ |
__________________ ________________________ _______________________ |
| M-STO #1 ← 1 | | RQ and M-STO #1 & #2 | |¬M-STO #1 |M-STO #1 |
| M-STO #2 ← 0 |.......| will be turned off |..... | | |
| M-STO RQ ← 1 | | when cycle taken. | . ↓ ↓ |
__________________ ________________________ . ________________ __________________ |
| . | M-STO #1 ← 0 | | wait one cycle | |
| ......| M-STO #2 ← 1 | __________________ |
| | M-STO RQ ← 1 | | |
| ________________ ---------------
| |
| |
| |
| |
| |
|read cycle now done |read cycle now done
|for this mem (bus) |for this mem (bus)
| |
| |
------------------------------------------------------------
|
_______________
BOTH DONE
_______________
|
|
↓
__________________
| DOING READ ← 0 |
__________________
|
|
_________________________
| |
|¬GONNA DO WRITE |GONNA DO WRITE
| |
↓ ↓
____________________ ____________________
| MEM INT FREE ← 1 | | DOING WRITE ← 1 |
____________________ | (see MEM CONTROL |
| | WRITE CYCLE) |
| ____________________
| |
| |
------------→|←------------
↓
___
/ \
| END |
\___/