perm filename FL2[1,PMP] blob
sn#019780 filedate 1973-01-12 generic text, type T, neo UTF8
____________
| START |
| HERE | ___________________________
| | | Types of cycles: |
____________ | DUMP-2 M-STO |
| | C-I/O E-FET |
↓ | MAP-CY ST-CHK |
__________________________________ | CACHE-DUMP I-FET |
| Type-of-cycle Requests stable |........| READ-AROUND E-STO |
__________________________________ ___________________________
|
↓
______________________ __________________________________
| Solve type-of-cycle | | Accept E-STO and ST-CHK RQ's | _____________________________
| priority. |..........| only if Memory interface | | Accept I/O RQ's only if |
| {latch -- B1C0} | | (control) is free and the last |........| the last cycle was not |
_______________________ | cycle was not an I-FET or E-FET| | an I/O cycle that missed. |
| | or ST-CHK that missed. | _____________________________
| | (otherwise ignore these RQ's) |
| __________________________________
|
| ___________________________________________________
| | Cycles which use SMA or IMA may indicate |
| | that only the low order 4 bits should come from |
| ...........| SMA or IMA. Rest of address comes from AC |
| . | pointer A or B. |
↓ . ___________________________________________________
__________________
| Select |_________________________________________________________________________________________________
| Address | | | | | | | | | |
__________________ |DUMP-2 |C-I/O |CACHE-DUMP |MAP-CY |READ-AROUND |I-FET |E-STO |ST-CHK |E-FET
| ↓∨ M-STO | ↓ ---- | ↓ | | |
| __________________ | ___________________ | | _______________ | | |
| | from | | | from C-D | | | | from APCL | | ___________ |
| | FETCH Register | | | Address | | | | (I-BOX) | | | | |
| |-------- | | |------- | | | _______________ | |ST-CHK |ST-CHK |
| | if DUMP-2 then | | | if "DUMP-NOT- | | | | |from |from |
| | invert bit 34. | | | DONE"(from last | | | | |SMA |IMA |
| | if M-STO ∧ | | | cycle): | | | ↓ ↓ ↓ ↓
| | M-STO #1 then | | | Direct from C-D | | | ______________ ________________
| | bit 34 = 0. | | | register. | | ↓ | from SMA | | from IMA |
| | if M-STO ∧ | | | if "¬DUMP-NOT- | | ________________ | register | | (I-BOX) |
| | M-STO #2 then | | | DONE": | | | (no address | ______________ ________________
| | bit 34 = 1. | | | from C-D reg. | | | needed) |
| __________________ | | plus 1(in bit | | ________________
↓ | | 33; i.e. | |
___________________ ↓ | plus 4) | |
| hold selected | ____________ ___________________ |
| address in CAL | | from I/O | ↓
| {latch C1A0} | | address | ___________
_____________________ ____________ | from FA |
| memory (cache) | | (MAP) |
| starts to select | ___________
| addressed word. |
_____________________
|
|
|
↓
________________________
| set C-D OPER |_______________________________
| according to whether | | |
| or not this is a | |ELSE |CACHE-DUMP
| CACHE-DUMP type of | | |∨ DUMP-2 ∧ CACHE-DUMP(on last cycle)
| cycle. | | |
________________________ ↓ ↓
| ________________ ________________
| | C-D OPER ← 0 | | C-D OPER ← 1 |
| ________________ ________________
|
|
|
|____________________________
| |
|¬CACHE-DUMP |CACHE-DUMP
| |
| ↓
| _________________________________________
| | if "¬DUMP-NOT-DONE"(from last cycle): |
| | increment CACHE-DUMP register by 1 |
| | (in bit 33; i.e. by 4) |
| _________________________________________
| |
| |
|←-----------------------------
|
↓
________________
| select cache |_______________________________________________________________________________→ else no matter
| input data. | | | |
| {by A0} | |M-STO |READ-AROUND |E-STO
________________ | | |
| ______________ _______________ |
↓ | | | | ↓
________________ |M-STO #1 |M-STO #2 |fetch |fetch _________________
| load CAL LB | | -------¬ |register |register | E-BOX |
| SPECIAL from | ↓ ↓----------------+----- 34(0) ↓34(1) | store data |
| CAL 35 {A} | ____________ | ____________ | (one register |
________________ | BUS 0 | ----------→| BUS 1 | | to both words)|
| | data | | data | _________________
↓ | (2 words)| | (2 words)|
______________ ____________ ____________
| load |
| USE-BIT CAL|
| {A0} |
_____________________
| use-bit memory |
| starts to select |
| addressed bits. |
_____________________
|
|
↓
____________________
| load PASS-AROUND |
| LATCH (PAL) |____________________________________
| {AB0} | |FETCH register 35(0) |FETCH register 35(1)
____________________ | |
| ↓ ↓
| _________________________ _________________________
| | from CACHE STORE DATA | | from CACHE STORE DATA |
| | EVEN WORD | | ODD WORD |
| _________________________ _________________________
|
|
|________________________
| |
|¬READ-AROUND |READ-AROUND
| |
| ↓
| ______________________
| | READ-AROUND RQ←0 |
| ______________________
| |
|←-----------------------
|____________________
| |
|¬M-STO |M-STO
| |
| ↓
| _______________________
| | Do write cycle in |
| | appropriate parts |
| | of Cache: in all |_____________________________________________________________
| | cases, do write in | | | | | |
| | only the memory | |(M-STO#1 | |(M-STO#2 | |M-STO NEW ADDRS
| | selected by "M-STO | |∧ #0 M-WRITE OK) | |∧ #2 M-WRITE OK) | |
| | MEM-SEL" register. | |∨ M-STO NEW ADDRS | |∨ M-STO NEW ADDRS | |
| _______________________ | | | | |
| | | ----------------- | -------------- |
| | | | | | |
| | | |(M-STO#1 | |(M-STO#2 |
| | | |∧ #1 M-WRITE OK) | |∧ #3 M-WRITE OK) |
|←----------------- | |∨ M-STO NEW ADDRS | |∨ M-STO NEW ADDRS |
| | ↓ | ↓ |
| | _____________________ | _____________________ |
| | | Do write in ODD | | | Do write in ODD | |
| | | half of data part | | | half of data part | |
| | | and addrs WORD #1 | | | and addrs WORD #3 | |
| ↓ _____________________ ↓ _____________________ ↓
| _____________________ _____________________ ______________________
| | Do write in EVEN | | Do write in EVEN | | Do write in addrs |
| | half of data part | | half of data part | | WORDS #0,1,2,3. |
| | and addrs word #0 | | and addrs WORD #2 | ______________________
| _____________________ _____________________
|
|
|_____________________
| |
|¬E-STO |E-STO
| |
| ↓
| ____________________________
| | Do write in appropriate |
| | parts of Cache: in all |__________________________________________________________
| | cases, do write in only | | |
| | the memory selected by | |E-STO ADDRS 35(0) |E-STO ADDRS 35(1)
| | "E-STO MEM-SEL" register | |∨ E-STO NEW ADDRS |∨ E-STO NEW ADDRS
| ____________________________ ↓ ↓
| | _____________________ _____________________
| | | Do write in EVEN | | Do write in ODD |
|←--------------------- | word of data part | | word of data part |
| _____________________ _____________________
| | |
| | |
| __________________________ _______________________
| |E-STO ADDRS 34(0) |E-STO ADDRS 34(1) |E-STO ADDRS 34(0) |E-STO ADDRS 34(1)
| |∨ E-STO NEW ADDRS |∨ E-STO NEW ADDRS |∨ E-STO NEW ADDRS |∨ E-STO NEW ADDRS
| ↓ ↓ ↓ ↓
| _________________ _________________ _________________ _________________
| | Do write in | | Do write in | | Do write in | | Do write in |
| | addrs WORD #0 | | addrs WORD #1 | | addrs WORD #2 | | addrs WORD #3 |
| _________________ _________________ _________________ _________________
|
↓
_____________________
| Set up gating on |
| Cache Output Data |_______________________________________
| Latches. | |Read-Around(late) |
_____________________ |∨ (E-STO(late) |ELSE
| |∧ Store-Through(late)) |
| | |
| ↓ _________________________
| ___________________ | |
| | CODL EVEN ← PAL | |CAL LB SPECIAL(0) |CAL LB SPECIAL(1)
| | CODL ODD ← PAL | | |
| ___________________ | |
↓ ↓ ↓
____________________________ _________________________ _________________________
| USE-BITs and #x INVALID | | CODL EVEN ← 4x72 EVEN | | CODL EVEN ← 4x72 ODD |
| bits come out of use-bit | | CODL ODD ← 4x72 ODD | | CODL ODD ← 4x72 EVEN |
| mem {B0} | _________________________ _________________________
____________________________
|
|
↓
____________________________________
| Address comes out of Map and |
| addresses and NEEDWRITE bits and |
| Mx Wy INVALID bits come out of |
| addrs part of Cache. |
| {late B0} |
____________________________________
|
| __________________________________________
↓ | DUMP-NOT-DONE |
_____________________________________ | ← [(M0 W0 NEEDWRITE ∨ M0 W1 NEEDWRITE |
| form DUMP-NOT-DONE as: | | ∨ M0 W2 NEEDWRITE ∨ M0 W3 NEEDWRITE) |
| the OR of all the Mx Wy NEEDWRITE | | ∧ (¬UB00 ∨ ¬UB01) ∧ ¬#0 INVALID] |
| bits for all y (0 to 3) and for |...........| ∨ [(M1 W0 NEEDWRITE ∨ M1 W1 NEEDWRITE |
| all x such that (¬#x INVALID and | | ∨ M1 W2 NEEDWRITE ∨ M1 W3 NEEDWRITE) |
| use bits ≠3.) | | ∧ (¬UB10 ∨ ¬UB11) ∧ ¬#1 INVALID] |
_____________________________________ | ∨ [(M2 W0 NEEDWRITE ∨ M2 W1 NEEDWRITE |
| | ∨ M2 W2 NEEDWRITE ∨ M2 W3 NEEDWRITE) |
| | ∧ (¬UB20 ∨ ¬UB21) ∧ ¬#2 INVALID] |
| | ∨ [(M3 W0 NEEDWRITE ∨ M3 W1 NEEDWRITE |
| | ∨ M3 W2 NEEDWRITE ∨ M3 W3 NEEDWRITE) |
| | ∧ (¬UB30 ∨ ¬UB31) ∧ ¬#3 INVALID] |
| __________________________________________
|
|
↓ __________________________________________________________________________________
__________________________ | if ¬C-I/O ∧ ¬ST-CHK: | NOTE: if "DOUBLE FETCH" is |
| Form selected INVALID |.......| for x=0,1,2,3: | true (and ¬C-I/O ∧ ¬ST-CHK) then: |
| signals. | | if CAL 34, CAL 35=y (0 to 3): | if CAL 34(0): |
__________________________ | select→ | Mx INVALID=Mx W0 INVALID ∨ Mx W1 INVALID |
| | Mx INVALID=Mx Wy INVALID | if CAL 34(1): |
| | if C-I/O ∨ ST-CHK: | Mx INVALID=Mx W2 INVALID ∨ Mx W3 INVALID |
| | Mx Wy INVALID ← 0 for all x. |________________________________________________
| __________________________________
|
↓
________________________ ________________________________________________
| select by word the | | if x = mem for which use-bits = 3: |
| NEEDWRITE bits based |................| Wy NEEDWRITE ← Mx Wy NEEDWRITE ∧ ¬#X INVALID |
| on use-bits =3. | | for y = 0,1,2,3. |
________________________ ________________________________________________
|
|
| _______________________________________________
↓ | Set NEEDWRITE = (OR of Wx NEEDWRITE for |
_______________________ | x=1 to 3) |
| form NEEDWRITE and | | Set NEED DUMP-2 as follows: |
| NEED-DUMP-2 signals |..............| if CAL 34(0): |
_______________________ | NEED DUMP-2←W2 NEEDWRITE ∨ W3 NEEDWRITE |
| | if CAL 34(1): |
| | NEED DUMP-2←W0 NEEDWRITE ∨ W1 NEEDWRITE |
| _______________________________________________
|
↓ ________________________________________________________
_________________ | for x=0,1,2,3: |
| Form HIT/MISS |.........| if (addrs-out of Map)=(addrs out of Cache, #x) |
| signals. | | ∧ ¬#x INVALID ∧ ¬C-D OPER |
| {formed by | | then #x ADDRS HIT←1; else #x ADDRS HIT←0. |
| middle B1} | |----------- |
_________________ | #x VAL HIT←#x ADDRS HIT ∧ ¬Mx INVALID |
| |----------- |
| | #x VAL/ADDRS MISS←¬#x VAL/ADDRS HIT |
| |----------- |
| | If all VAL HITs are false then "VAL HIT"←0 else 1. |
| | If all ADDRS HITs are false then "ADDRS HIT←0 |
| | else 1. |
| |------------ |
| | Create "#x ADDRS HIT(L)" as follows: |
| | If ADDRS HIT → #x ADDRS HIT(L)← #xADDRS HIT |
| | If ADDRS MISS → #x ADDRS HIT(L)←1 for x= the |
| | Memory with use-bits =3, ←0 for other x's. |
| |----------------- |
| | Note: if C-D OPER: |
| | all HITs are false and all MISS's are true. |
| | except #x ADDRS HIT(L) which will be true for |
| | the memory with use-bits =3. (others false) |
| ________________________________________________________
|
|
↓
__________________________________ ______________________________________________________
| Select 2 of the 8 data words | | This selects the 2 words for which the address |
| from the Cache (4x72) based on |......| matched if there was a match, otherwise it selects |
| #x ADDRS HIT(L). | | 2 words with associated use bits =3. |
__________________________________ ______________________________________________________
|
|
↓ ___________________________________________________
__________________________ | use-bit update algorithm: |
| form updated use-bits. |___________| use #x ADDRS HIT(L) to select the use bits for |
__________________________ | the mem that hit. Let these use bits = y. (Note |
| | that if ADDRS MISS is true, y=3, because |
| | #x ADDRS HIT(L) will be true for the x with use |
| | bits =3). |
| | Then let mem z use-bits = w. |
| | Updated w ← if w<y then w+1; |
| | if w>y then w; |
| | if w=y then 0. |
| ___________________________________________________
|
|
|
↓
_______________________ ________________________________
| Select by word the | | if #x ADDRS HIT(L) is true: |
| VALID |............| Wy VALID←¬Mx Wy INVALID |
| bits based on #x | | for y=0,1,2,3. |
| ADDRS HIT(L). | ________________________________
_______________________
|
|
↓
__________________
| latch CODL |
| {B1C0} |
__________________
|
|
|______________________________________________________
| | |
|ELSE |(I-FET ∨ E-FET) |ST-CHK(LATE)
| |∧ MEM INT FREE |∨ ST-CHK ON FETCH
| | |
| | |
| ↓ ↓
| ______________________________________ ___________________________
| | load "M-STO MEM-SEL" register | | load "E-STO MEM-SEL and |
| | from #x ADDRS HIT(L) | | "E-STO NEW ADDRS" |
| | as: for x=0 to 3: | | as for "M-STO ...." |
| | M-STO MEM-SEL #x ← #x ADDRS HIT(L) | | ←←←(see at left) |
| |--------- | | |
| | load #x M-WRITE OK from Wx VALID | ___________________________
| | as: for x=0 to 3: | |
| | #x M-WRITE OK ← ¬Wx VALID | |
| |--------- | |
| | If ADDRS MISS then | |
| | M-STO NEW ADDRS←1 else 0 | |
| ______________________________________ |
| | |
|←-----------------------←---------------------------------
|
|
|
|
|________________________________________________________________________
| | |
|ELSE |(I-FET ∨ E-FET ∨ CACHE-DUMP ∨ ST-CHK) |STORE-THROUGH
| |∧ MEM INT FREE (LATE) |∧ E-STO
| | |
| | |
| ↓ ↓
| _________________________________________________ ______________________________
| | Set "WRITE Wx" as: | | Set "WRITE Wx" as: |
| | WRITE Wx←Wy NEEDWRITE | | if CAL 34(0): |
| | With x & y from one of the following tables: | | WRITE W0←1 all others ←0 |
| | ___________________________________________ | | if CAL 34(1): |
| | |if CAL LB SPECIAL(0) | if CAL LB SPECIAL(1)| | | WRITE W2←1 all others ←0 |
| | | x y | x y | | | |
| | | 0 0 | 0 1 | | ______________________________
| | | 1 1 | 1 0 | | |
| | | 2 2 | 2 3 | | |
| | | 3 3 | 3 2 | | |
| | |___________________________________________| | |
| | | |
| _________________________________________________ |
| | |
| | |
|←-------------------------------←-----------------------------------------
|
|
|
|______________________________________
| |
|MEM INT BUSY(LATE) |MEM INT FREE(LATE)
| |
| ↓
| ________________________________________
| | Load FETCH REGISTER from CAL (18-35) |
| | {B} |
| | |
| | Load MEM READ ADDRS from MAP (16-26) |
| | {C0} |
| ________________________________________
| |
|←-------------------------------
|
|_______________________________
| |
|ELSE |(I-FET ∨ E-FET ∨ ST-CHK ∨ CACHE-DUMP)
| |∧ MEM INT FREE
| ↓
| ____________________________________
| | load MEM WRITE ADDRS register |
| | from ADDRS OUTPUT of ADDRS part |
| | of CACHE, selcted by USE-BITS =3 |
| | {C0} |
| ____________________________________
| |
| |
|←-------------------------------
|
|____________________________________
| |
|¬ST-CHK(LATE) |ST-CHK(LATE)
| |
| ↓
| ____________________________________________
| | Load S-C ADDRS REGISTER from CAL (16-26) |
| | {C0} |
| ____________________________________________
| |
| |
|←-----------------------------------
|
|
|_______________________________________
| |
|ELSE |MEM INT FREE(LATE) ∧ (I-FET ∨ E-FET)(LATE)
| |∧ VAL MISS ∧ ¬FETCH ABORT ∧ ¬MAP MISS
| |
| ↓
| ___________________________________
| | Set memory control flags: |
| | DOING READ ← 1 |
| | MEM 0 RQ ← 1 |
| | MEM 1 RQ ← 1 |
| | MEM INT FREE ← 0 |
| | (see mem control flow chart for |
| | continuation of fetch) {C0} |
| ___________________________________
| |
| |
| ______________________________
| | |
| |¬ADDRS MISS |ADDRS MISS
| |∨ ¬NEEDWRITE |∧ NEEDWRITE
| | |
| | ↓
|←------------------ ____________________________
| | set memory control flag: |
| | GONNA DO WRITE ← 1 |
| | {C0} |
| ____________________________
| |
| |
|←------------------------------------------
|
|
|_______________________________________
| |
|ELSE |(E-STO(LATE) ∧ STORE-THROUGH(LATE))
| |∨ (ST-CHK(LATE) ∧ ADDRS MISS ∧ NEDWRITE ∧ ¬MAP MISS)
| |∨ (MEM INT FREE(LATE) ∧ CACHE-DUMP(LATE) ∧ NEEDWRITE)
| ↓
| _______________________________
| | set memory control flags: |
| | DOING WRITE ← 1 |
| | MEM INT FREE ← 0 |
| | (see mem control flow chart |
| | for continuation) {C0} |
| _______________________________
| |
| |
|←--------------------------------------
|
|
|
|___________________________________
| |
|ELSE |(I-FET ∨ E-FET ∨ ST-CHK ∨ CACHE-DUMP)(LATE)
| |∧ MEM INT FREE(LATE)
| |∧ NEED DUMP-2
| |∧ ¬MAP MISS
| |∧ ADDRS MISS
| |
| ↓
| ___________________________
| | DUMP-2 RQ on next cycle |
| ___________________________
| |
| |
|←----------------------------------
|
|
|
|__________________________________
| |
|ELSE |[(I-FET ∨ E-FET ∨ ST-CHK ∨ CACHE-DUMP)
| |∧ ¬DUMP-2 (on next cycle)]
| |∨ [ DUMP-2
| |∧ (I-FET ∨ E-FET ∨ ST-CHK ∨ CACHE-DUMP)(on last cycle)]
↓ |
________________ ↓
| USE-BITS | __________________________
| Don`t change.| | write updated USE-BITs |
________________ | {C1} |
| __________________________
| |
| |
|←---------------------------------
|
|
|______________________
| |
|ELSE |M-STO
| |∨ E-STO ∨ CACHE-DUMP
| |∨[DUMP-2 ∧ CACHE-DUMP (on last cycle)
| |∨ C-I/O
| |
↓ ↓
______________ _______________________
| #x INVALD | | write selected |
| bits don't | | #x INVALID bits |_____________________________________________________________________
| change. | | (if any). | | | | |
______________ | (maybe none change) | |M-STO ∨ E-STO |C-I/O(late) |[CACHE-DUMP (LATE) |CACHE-DUMP
| | {C1} | | |∧ I/O INVALIDATE |∧ ¬DUMP-2 (next cycle)] | (LATE)
| _______________________ | | (from I/O |∨ [DUMP-2 (LATE) |∧ ¬DUMP-
| | | | control) |∧ CACHE-DUMP(last cycle)] | NOT-DONE
|←--------------------- ↓ | | |
| _____________________ ↓ ↓ ↓
| | write #x INVALID | ____________________ ____________________ ____________________
| | as "VALID" for | | write #x INVALID | | write #x INVALID | | write #x INVALID |
| | the x selected | | as "INVALID" for | | as "INVALID" for | | as "INVALID" for |
| | by "E-STO MEM-SEL"| | the x for which | | the x for which | | the three x's |
| | or "M-STO MEM-SEL"| | #x ADDRS HIT is | | #x ADDRS HIT(L) | | for which |
| | depending on type | | true (if any). | | is true. Others | | #x ADDRS HIT(L) |
| | of cycle. | | Others don't | | probably don't | | is not true. |
| | Don't change | | change. | | change. (see at | | Other x may or |
| | #x INVALID for | ____________________ | right). | | may not change |
| | other x's. | ____________________ | (see at left). |
| _____________________ ____________________
|
|
|
|
|__________________________________________________________
| | |
|ELSE |E-STO(LATE) |DUMP-2(LATE)
| |∧ STORE-THROUGH(LATE) |∨ ((I-FET ∨ E-FET ∨ ST-CHK ∨ CACHE-DUMP)(LATE)
| | | ∧ MEM INT FREE)
| | |
| | _________________________________
| | | |
| | | CAL 34(0) |CAL 34(1)
| | | |
| -----------------+-----+------------------------| |
| | | | |
| ↓ ↓ ↓ ↓
| __________________________ __________________________
| | Strobe cache data into | | Strobe cache data into |
| | store buffers. | | store buffers. |
| | BUF 0 ← CODL EVEN | | BUF 2 ← CODL EVEN |
| | BUF 1 ← CODL ODD | | BUF 3 ← CODL ODD |
| |{C1A} | | {C1A} |
| __________________________ __________________________
| | |
| | |
|←------------------------------------←-------------------------------
|
|
_____ _____________________
/ \ | At this point you |
| END |...........| are part way into |
\ / | the next cycle. |
----- _____________________