perm filename EE315[1,VDS]1 blob sn#191739 filedate 1975-12-12 generic text, type C, neo UTF8
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C00011 00003				TEST  DATA
C00012 ENDMK

			by Victor Scheinman

	This report covers  the design and test  of a DVM using  an 8
bit DAC an analog voltage comparator and an 8080 based microprocessor

	The method used  to carry  out the conversion  of the  analog
voltage to  the digital  display output is  the method  of successive
approximation.   This procedure involves comparing the unknown analog
voltage with  fixed voltages  whose increments differ  by factors  of
two.   Thus, by performing only  8 tests, the unknown  voltage can be
determined to a resolution of 8 bits (one part in 256).

	The fixed  reference  voltages  are  produced  by  an  8  bit
integrated circuit digital  to analog converter.   The 8  bit digital
signals  applied  to  this device  are  generated  by  an 8080  based
microcomputer, having one 8 bit output port dedicated to driving this
DAC.   The reference  and unknown  signals are  compared by  an LM311
comparator.  The TTL level comparator output is entered as one bit of
the system's single 8-bit input port.

	The  following subsystems  were  designed  and  developed  in
completing this project.

	An 8080 microprocessor  based minimal system.  This consisted
of an 8080  chip, a 8212  status latch for  storing processor  status
information during each machine cycle, an 8212  8-bit output port, an
8212 8-bit input port (only one bit of which was used), a 1702 (256 x
8) PROM  for program  storage, two  8101(256 x  4)  static RAM's  for
temporary data  storage, and  an 8212  memory buffer  for controlling
data out of the PROM and RAM's.

	A  2 mhz clock generator was built  using two 7410 NAND gates
operating as inverting buffers with suitable resistors and capacitors
to make them a free  running astable multivibrator. Using a couple of
7473 type JK flip-flops  this 2 mhz output  was converted into a  500
khz 2-phase clock with the timing and duty cycle suitable for running
the 8080.

	The DAC was a Motorola MC1408L 8-bit current output DAC. This
DAC was addressed directly from  the 8-bit output port. In  addition,
the output  port addressed  8 LED's  acting as the  DVM display.   In
single step  mode, these LED's acted as displays of the status of the
Data Bus (by manually enabling the output port latch).

	A National LM311 comparator was used to compare the reference
and unknown  signals.  Its output  was TTL level  conditioned and fed
into the #1 bit of the input port.

	Control  of  the  system  was  accomplished  by  providing  a
RUN-STEP switch, a SINGLE STEP pushbutton switch, and a RESET switch.
To effect the  proper timing of the control signals, the RUN and STEP
functions were clocked by TTL level clock signals.


	Each subsystem was tested  separately.  Clock waveforms  were
checked on a scope.  Switch  functions were next tested.  The minimal
system  was brought up using a JMP  00H programmed PROM.  Testing the
system with this program revealed a defective ready line in the 8080.
A check with another chip verified proper single step operation.

	The  DAC and  comparator were  tested separately  by manually
setting up data  on the  output port and  clocking it  into the  DAC.
Proper  operation of  the  comparator was  obtained  by providing  an
offset  adjustment  potentiometer to  essentially  scale  the unknown
input to a comparable value.

	Finally, software was written and the total operation  of the
system verified.


	In  short, the  system worked.   Two  performance tests  were

Test 1.   An analog voltage between 1 and 7 volts was applied.  Table
1 shows the digital output.  By differencing the  digital output, the
linearity of  the system was checked.   This data indicated linearity
to 1 LSB throughout the range of voltages applied.

Test 2.   The basic  frequency generator (2  mhz- for  all the  above
work)  was  replaced  by  a  square   wave  generator.  System  clock
frequencies  from 500khz  to 2.5  mhz were tried.   This  second test
records data obtained while operating at 2.5 mhz.  It turns  out that
the linearity of  the system remains about the same,  but the data is
offset by  about 4 counts. As the program outputs a test value on one
instruction and inputs the comparator signal on the next, it would be
expected  that  the  shift could  be  caused  by  the shorter  timing
interval.  As an IN and  OUT instruction each take 10 clock  periods.
The shortened timing interval  is about 4 usecs.  From  the LM311 and
MC1408  data sheets, this should  still be more than  enough time for
DAC and comparator  settling to occur.   More tests  are in order  to
determine  the real  causes  of this  shift.   Interestingly  enough,
although  rated  at 2  mhz  max.   clock, the  8080  apparantly still
operated well at 2.5 mhz.


	An 8080  microprocessor DVM  system was  designed, built  and
tested.     Although  operating  with  a  minimal   system,  the  DVM
demonatrated its ability to properly digitize an analog signal having
a range of  values from 1 to 7  vdc.  With a more  elaborate program,
additional data  processing could be performed to  enable this DVM to
be used as a simple data acquisition and processing system.  et


Test	Analog signal 	Digital value	Decimal equiv.	Difference

1	7 vdc.		11110010	242		
	6		11100000	224		18
	5		11001101	205		19
	4		10111010	186		19
	3		10101000	168		18
	2		10010101	149		18
	1		10000011	131		18

2	7		11110110	246		
	6		11100011	227		19
	5		11010000	208		19
	4		10111110	190		18
	3		10101010	170		20
	2		10011000	152		18
	1		10000110	134		18

Notes:  Tests 1 and 2 were the same execpt test 1 clock =500 khz.,
test 2 clock = 2.5 mhz.